/* SPDX-License-Identifier: GPL-2.0+ */
// $Module: reg_RTC_IP_MUX $
// $RegisterBank Version: v1.0.00 $
// $Author:  $
// $Date: Tue, 28 Feb 2023 09:50:51 AM $
//

//GEN REG ADDR/OFFSET/MASK
#define  RTC_IP_MUX_REG_GRP_CLK_25M_OUT_SEL  0x0
#define  RTC_IP_MUX_REG_GRP_GPIO119_SEL  0x4
#define  RTC_IP_MUX_REG_GRP_PLL_LOCKO_SEL  0x8
#define  RTC_IP_MUX_REG_GRP_CAM_MCLK0_SEL  0xc
#define  RTC_IP_MUX_REG_GRP_UART0_TX_SEL  0x10
#define  RTC_IP_MUX_REG_GRP_UART0_RX_SEL  0x14
#define  RTC_IP_MUX_REG_GRP_UART4_TX_SEL  0x18
#define  RTC_IP_MUX_REG_GRP_PWM16_SEL  0x1c
#define  RTC_IP_MUX_REG_GRP_IIC3_SDA_SEL  0x20
#define  RTC_IP_MUX_REG_GRP_A53_JTAG0_TDO_SEL  0x24
#define  RTC_IP_MUX_REG_GRP_UART4_RX_SEL  0x28
#define  RTC_IP_MUX_REG_GRP_PWM17_SEL  0x2c
#define  RTC_IP_MUX_REG_GRP_IIC3_SCL_SEL  0x30
#define  RTC_IP_MUX_REG_GRP_A53_JTAG0_TCK_SEL  0x34
#define  RTC_IP_MUX_REG_GRP_UART3_TX_SEL  0x38
#define  RTC_IP_MUX_REG_GRP_PWM18_SEL  0x3c
#define  RTC_IP_MUX_REG_GRP_A53_JTAG0_TDI_SEL  0x40
#define  RTC_IP_MUX_REG_GRP_UART3_RX_SEL  0x44
#define  RTC_IP_MUX_REG_GRP_PWM19_SEL  0x48
#define  RTC_IP_MUX_REG_GRP_A53_JTAG0_TMS_SEL  0x4c
#define  RTC_IP_MUX_REG_GRP_I2S2_MCLK_SEL  0x50
#define  RTC_IP_MUX_REG_GRP_CAM_MCLK1_SEL  0x54
#define  RTC_IP_MUX_REG_GRP_UART3_RTS_SEL  0x58
#define  RTC_IP_MUX_REG_GRP_A53_JTAG0_TRST_X_SEL  0x5c
#define  RTC_IP_MUX_REG_GRP_I2S1_MCLK_SEL  0x60
#define  RTC_IP_MUX_REG_GRP_UART7_TX_SEL  0x64
#define  RTC_IP_MUX_REG_GRP_UART3_CTS_SEL  0x68
#define  RTC_IP_MUX_REG_GRP_A53_JTAG0_SRST_X_SEL  0x6c
#define  RTC_IP_MUX_REG_GRP_CAM_MCLK2_SEL  0x70
#define  RTC_IP_MUX_REG_GRP_UART7_RX_SEL  0x74
#define  RTC_IP_MUX_REG_GRP_IIC1_SDA_SEL  0x78
#define  RTC_IP_MUX_REG_GRP_CAM_MCLK3_SEL  0x7c
#define  RTC_IP_MUX_REG_GRP_WG1_D0_SEL  0x80
#define  RTC_IP_MUX_REG_GRP_IIC1_SCL_SEL  0x84
#define  RTC_IP_MUX_REG_GRP_CAM_MCLK4_SEL  0x88
#define  RTC_IP_MUX_REG_GRP_WG1_D1_SEL  0x8c
#define  RTC_IP_MUX_REG_GRP_IIC2_SDA_SEL  0x90
#define  RTC_IP_MUX_REG_GRP_CAM_MCLK5_SEL  0x94
#define  RTC_IP_MUX_REG_GRP_IIC2_SCL_SEL  0x98
#define  RTC_IP_MUX_REG_GRP_CAM_MCLK6_SEL  0x9c
#define  RTC_IP_MUX_REG_GRP_SEL_CLK_25M_OUT   0x0
#define  RTC_IP_MUX_REG_GRP_SEL_CLK_25M_OUT_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_CLK_25M_OUT_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_CLK_25M_OUT_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_GPIO119   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_GPIO119_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_GPIO119_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_GPIO119_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_PLL_LOCKO   0x8
#define  RTC_IP_MUX_REG_GRP_SEL_PLL_LOCKO_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_PLL_LOCKO_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_PLL_LOCKO_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK0   0xc
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK0_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK0_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK0_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_UART0_TX   0x10
#define  RTC_IP_MUX_REG_GRP_SEL_UART0_TX_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_UART0_TX_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_UART0_TX_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_UART0_RX   0x14
#define  RTC_IP_MUX_REG_GRP_SEL_UART0_RX_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_UART0_RX_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_UART0_RX_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_UART4_TX   0x18
#define  RTC_IP_MUX_REG_GRP_SEL_UART4_TX_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_UART4_TX_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_UART4_TX_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_PWM16   0x1c
#define  RTC_IP_MUX_REG_GRP_SEL_PWM16_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_PWM16_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_PWM16_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_IIC3_SDA   0x20
#define  RTC_IP_MUX_REG_GRP_SEL_IIC3_SDA_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_IIC3_SDA_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_IIC3_SDA_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TDO   0x24
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TDO_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TDO_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TDO_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_UART4_RX   0x28
#define  RTC_IP_MUX_REG_GRP_SEL_UART4_RX_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_UART4_RX_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_UART4_RX_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_PWM17   0x2c
#define  RTC_IP_MUX_REG_GRP_SEL_PWM17_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_PWM17_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_PWM17_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_IIC3_SCL   0x30
#define  RTC_IP_MUX_REG_GRP_SEL_IIC3_SCL_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_IIC3_SCL_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_IIC3_SCL_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TCK   0x34
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TCK_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TCK_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TCK_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_TX   0x38
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_TX_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_TX_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_TX_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_PWM18   0x3c
#define  RTC_IP_MUX_REG_GRP_SEL_PWM18_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_PWM18_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_PWM18_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TDI   0x40
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TDI_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TDI_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TDI_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_RX   0x44
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_RX_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_RX_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_RX_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_PWM19   0x48
#define  RTC_IP_MUX_REG_GRP_SEL_PWM19_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_PWM19_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_PWM19_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TMS   0x4c
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TMS_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TMS_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TMS_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_I2S2_MCLK   0x50
#define  RTC_IP_MUX_REG_GRP_SEL_I2S2_MCLK_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_I2S2_MCLK_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_I2S2_MCLK_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK1   0x54
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK1_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK1_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK1_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_RTS   0x58
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_RTS_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_RTS_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_RTS_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TRST_X   0x5c
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TRST_X_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TRST_X_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_TRST_X_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_I2S1_MCLK   0x60
#define  RTC_IP_MUX_REG_GRP_SEL_I2S1_MCLK_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_I2S1_MCLK_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_I2S1_MCLK_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_UART7_TX   0x64
#define  RTC_IP_MUX_REG_GRP_SEL_UART7_TX_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_UART7_TX_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_UART7_TX_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_CTS   0x68
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_CTS_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_CTS_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_UART3_CTS_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_SRST_X   0x6c
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_SRST_X_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_SRST_X_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_A53_JTAG0_SRST_X_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK2   0x70
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK2_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK2_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK2_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_UART7_RX   0x74
#define  RTC_IP_MUX_REG_GRP_SEL_UART7_RX_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_UART7_RX_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_UART7_RX_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_IIC1_SDA   0x78
#define  RTC_IP_MUX_REG_GRP_SEL_IIC1_SDA_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_IIC1_SDA_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_IIC1_SDA_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK3   0x7c
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK3_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK3_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK3_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_WG1_D0   0x80
#define  RTC_IP_MUX_REG_GRP_SEL_WG1_D0_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_WG1_D0_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_WG1_D0_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_IIC1_SCL   0x84
#define  RTC_IP_MUX_REG_GRP_SEL_IIC1_SCL_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_IIC1_SCL_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_IIC1_SCL_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK4   0x88
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK4_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK4_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK4_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_WG1_D1   0x8c
#define  RTC_IP_MUX_REG_GRP_SEL_WG1_D1_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_WG1_D1_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_WG1_D1_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_IIC2_SDA   0x90
#define  RTC_IP_MUX_REG_GRP_SEL_IIC2_SDA_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_IIC2_SDA_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_IIC2_SDA_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK5   0x94
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK5_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK5_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK5_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_IIC2_SCL   0x98
#define  RTC_IP_MUX_REG_GRP_SEL_IIC2_SCL_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_IIC2_SCL_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_IIC2_SCL_BITS   0x4
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK6   0x9c
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK6_OFFSET 0
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK6_MASK   0xf
#define  RTC_IP_MUX_REG_GRP_SEL_CAM_MCLK6_BITS   0x4
